1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM), and particularly to a three-transistor type DRAM with a refresh circuit.
2. Description of the Prior Art
Three-transistor type memory cell is conventionally used in constructing dynamic random access memories (DRAMs) in integrated circuits, and particularly in application-specific integrated circuits (ASICs). FIG. 1 shows a schematic diagram of the three-transistor memory cell 20 including a transistor M2 for storing an information signal, a transistor M1 responsive to a signal on a write word line WS for transferring a data signal from a buffer 22 to the transistor M2, and another transistor M3 responsive to a signal on a read word line RS for transferring the information signal to a sense amplifier 23. Compared to another conventional four-transistor type memory cells primarily used in static random access memories (SRAMs), the three-transistor DRAM cell has its relative simplicity in both design and operation due to the fact that it can be manufactured by existing logic processes and no extra complicated pumping circuits are required. Further, the readout operation in the three-transistor DRAM cell is non-destructive, and is suitable to be used as two-port random access memory cell.
More specifically, the three-transistor cell 20 is written to by placing an appropriate data value (or information signal) on a write bit line WD and asserting the write word line WS. The data is then retained as charge on capacitance (not shown) coupled to the gate of the transistor M2. When data reading is commencing, the read word line RS is first raised, and the storage transistor M2 is either on or off depending on the stored valued therein. In other words, the series connection of the transistors M2 and M3 pulls the read bit line RD low when a charge (i.e., data 1) is stored in the transistor M2; otherwise, the read bit line RD remains high when no charge (i.e., data 0) is stored in the transistor M2. Furthermore, Y decoding switch is usually used for selecting one path through which data is written in and readout, especially when the memory configuration becomes larger.
FIG. 2 shows a schematic diagram of a conventional three-transistor DRAM 100, which is disclosed in the background description of a U.S. Pat. No. 4,935,896 to Matsumura et al., and is hereby incorporated by reference. As shown in the figure, one additional AND gate 12 should be inserted before each write word line WWL to avoid turning on the write word line WWL whose corresponding Y switch is off. Otherwise, the floating write bit line WB will probably disturb the stored value in the un-written cell.
For the three-transistor type DRAM cells, since some gate circuits, such as the AND gates 12, for selecting a memory cell to which information signal is to be written is required, the scale of a memory circuit becomes large, thereby occupying more area. Moreover, because the gate circuit 12 generally includes complementary metal-oxide-semiconductor (CMOS) transistors, a latch-up effect may incurred, temporarily or permanently failing the memory circuit.
The aforementioned U.S. Patent proposes a folded bit line architecture in the write path, which can also be used to refresh the data stored in each cell. FIG. 3 shows a schematic diagram of the three-transistor DRAM 300, wherein a pair of write bit lines WB.sub.1 and WB.sub.2 is used. This scheme offers solutions preserving cell density, however at the cost of a more complex circuit design. Particularly, the floor plan in laying out the memory cells should be carefully arranged to avoid being heavily loaded by the write bit lines WB.sub.1 and WB.sub.2. Further, the sense amplifiers 30 do not work if the capacitance between write bit lines WB.sub.1 and WB.sub.2 is large enough and the signal difference therebetween becomes too small. Accordingly, a need has been arisen to invent a three-transistor DRAM keeping the advantage of high cell density and offering flexibility of floor plan.